1. Field of the Invention
The present invention relates to mask defect inspection for semiconductor devices. In particular, the invention is directed to a size checking method and apparatus for inspecting the finished dimensions (CD: critical dimensions) of a circuit pattern formed on a mask.
2. Description of the Related Art
A size measuring technology is described, for example, in Jpn. Pat. Appln. KOKAI Publication No. 5-216996. This publication discloses a size recognition apparatus employed in an automatic figure input system.
The size recognition apparatus reads a pattern under inspection by means of an image input section, and acquires image data on that pattern. On the basis of the read image data, the apparatus divides a line segment into thin components, so as to detect the center line of the line segment. Subsequently, the thin segments are spread in the direction perpendicular to the center line, beginning with the center line, thereby measuring the width of the line segment. This width measuring method is based on counting the pixels included in the image data.
Size measuring technology is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 8-54224, Published Japanese Patent 2503508 and Jpn. Pat. Appln. KOKAI Publication No. 10-284608 as well.
The circuit patterns formed on masks are miniaturized year after year. An exposure apparatus projects a circuit pattern of a mask on a semiconductor substrate, and transfers that circuit pattern to the semiconductor substrate. At the time of transfer, the mask has to be checked to see whether or not a semiconductor wafer circuit pattern is depicted accurately in accordance with a design pattern.
Even when the size measuring technology is applied, the exposure apparatus is limited in resolution, and this resolution limitation gives rise to the phenomenon wherein the measured size of a circuit pattern is smaller than the actual size of that circuit pattern. This problem becomes more marked in proportion to the size of the circuit pattern.
Under the circumstances, it is difficult to check whether or not a semiconductor wafer circuit pattern is formed accurately on a mask.